| ISBN: ISBN: 0-8186-7597-7
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| ISBN: ISSN: 1063-6757
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| ISBN: DOI: 10.1109/ICCAD.1996.569803
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| |
| description |
A scan-based BIST scheme is presented which guarantees complete
fault coverage with very low hardware overhead. A probabilistic
analysis shows that the output of an LFSR which feeds a scan path
has to be modified only at a few bits in order to transform the
random patterns into a complete test set. These modifications may be
implemented by a bit-flipping function which has the LFSR-state as
an input, and flips the value shifted into the scan path at certain
times. A procedure is described for synthesizing the additional
bit-flipping circuitry, and the experimental results indicate that
this mixed-mode BIST scheme requires less hardware for complete
fault coverage than all the other scan-based BIST approaches
published so far.
|
| publisher |
Institute of Electrical and Electronics Engineers
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| type |
Text
|
| Article in Proceedings
|
| source |
In: Proceedings of the ACM/IEEE International Conference on CAD-96
(ICCAD), San Jose, CA, November 1996, pp. 337-343
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| contributor |
Rechnerarchitektur (IFI)
|
| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
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| Mixed-Mode BIST
|